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Partial Order Reduction for Verification of Real-Time Components
Publication Type:
Conference/Workshop Paper
Venue:
Proceedings of the 5th International Conference on Formal Modelling and Analysis of Timed Systems, Lecture Notes in Computer Science 4763
Publisher:
Springer Verlag
Abstract
We describe a partial order reduction technique for a real-time
component model. Components are described as timed automata
with data ports, which can be composed in static structures of unidirectional
control and data flow. Compositions can be encapsulated as
components and used in other compositions to form hierarchical models.
The proposed partial order reduction technique uses a local time semantics
for timed automata, in which time may progress independently in
parallel automata which are resynchronized when needed. To increase
the number of independent transitions and to reduce the problem of
re-synchronizing parallel automata we propose, and show how, to use information
derived from the composition structure of an analyzed model.
Based on these ideas, we present a reachability analysis algorithm that
uses an ample set construction to select which symbolic transitions to
explore. The algorithm has been implemented as a prototype extension
of the real-time model-checker Uppaal. We report from experiments
with the tool that indicate that the technique can achieve substantial
reduction in the time and memory needed to analyze a real-time system
described in the studied component model.
Bibtex
@inproceedings{Hakansson1121,
author = {John H{\aa}kansson and Paul Pettersson},
title = {Partial Order Reduction for Verification of Real-Time Components},
editor = {Jean-Fran{\c{c}}ois Raskin and P.S. Thiagarajan},
pages = {211--226},
month = {October},
year = {2007},
booktitle = {Proceedings of the 5th International Conference on Formal Modelling and Analysis of Timed Systems, Lecture Notes in Computer Science 4763},
publisher = {Springer Verlag},
url = {http://www.es.mdu.se/publications/1121-}
}